1. Field of the Invention
The present invention relates to handling reset events in a bus bridge. In one example, the techniques of the present invention provide mechanisms for allowing either side of the bus bridge to reset independently without violating bus protocols.
2. Description of the Prior Art
A number of benefits have spurred efforts towards higher levels of system integration on a programmable chip. Integrating separate components such as processors and peripherals on a single integrated circuit allows compact system size, low power requirements, durability, high-performance, and low unit costs. Further, programmable logic allows custom logic in an integrated circuit while avoiding time-consuming and expensive engineering processes associated with designing ASICs.
Implementing a system on a programmable chip typically entails connecting various master components and slave components. In many instances, various master component and slave component support different bus protocols. In order to facilitate the integration of these components on the programmable chip, bridges are provided to connect components running disparate bus protocols. In one example, a bus bridge is provided between a processor using a bus protocol in a first clock domain and various peripherals using a different bus protocol in a second clock domain.
Many programmable logic chips can be reconfigured with a new design relatively quickly. In doing so, a component may require reconfiguration. However, such reconfiguration often requires the resetting of other components in the system. Depending on the state of activity (e.g., idle versus running) of the components on both sides of the bridge, the process of resetting safely a required component is difficult. Conventional reset techniques involve performing a system wide reset that would simultaneously place substantially all system components in a known state. However, a system wide reset may be unnecessarily disruptive. One example of a programmable chip having components supporting different bus protocols is the Excalibur line of devices available from Altera Corporation of San Jose, Calif. The Excalibur line of devices includes bidirectional bridges connecting hard coded logic to programmable logic components. The bidirectional bridges are synchronous to the clock domain that drives them; however, the embedded processor domain and the PLD domains are asynchronous. As such, the clock domain for each side of the bridge can be optimized for performance. However, managing system signals such as reset signals on a programmable chip with components running disparate bus protocols are often difficult.
Consequently, it is therefore desirable to provide improved methods and apparatus for handling reset events. More specifically, it is desirable to provide techniques and mechanisms for efficiently and effectively handling reset events.